On 10/06/2019 at 17:20, Codrin Ciubotariu - M19940 wrote:
> From: Codrin Ciubotariu <codrin.ciubota...@microchip.com>
>
> In clk_generated_determine_rate(), if the divisor is greater than
> GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned.
> If clk_generated_set_rate() will be called later with this wrong
> rate, it will return -EINVAL, so the generated clock won't change
> its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1.
>
> Fixes: 8c7aa6328947 ("clk: at91: clk-generated: remove useless divisor loop")
> Signed-off-by: Codrin Ciubotariu <codrin.ciubota...@microchip.com>
Yes:
Acked-by: Nicolas Ferre <nicolas.fe...@microchip.com>
Thanks for having fixed this Codrin. Best regards,
Nicolas
> ---
> drivers/clk/at91/clk-generated.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/at91/clk-generated.c
> b/drivers/clk/at91/clk-generated.c
> index 5f18847965c1..290cffe35deb 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -146,6 +146,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> continue;
>
> div = DIV_ROUND_CLOSEST(parent_rate, req->rate);
> + if (div > GENERATED_MAX_DIV + 1)
> + div = GENERATED_MAX_DIV + 1;
>
> clk_generated_best_diff(req, parent, parent_rate, div,
> &best_diff, &best_rate);
>
--
Nicolas Ferre
