> > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct mii_bus *bus, > int phyaddr, int phyreg) > > struct stmmac_priv *priv = netdev_priv(ndev); > > unsigned int mii_address = priv->hw->mii.addr; > > unsigned int mii_data = priv->hw->mii.data; > > - u32 v; > > - int data; > > u32 value = MII_BUSY; > > + int data = 0; > > + u32 v; > > > > value |= (phyaddr << priv->hw->mii.addr_shift) > > & priv->hw->mii.addr_mask; > > value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw- > >mii.reg_mask; > > value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) > > & priv->hw->mii.clk_csr_mask; > > - if (priv->plat->has_gmac4) > > + if (priv->plat->has_gmac4) { > > value |= MII_GMAC4_READ; > > + if (phyreg & MII_ADDR_C45) > > + stmmac_mdio_c45_setup(priv, phyreg, &value, &data); > > + } > > > > if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & > MII_BUSY), > > 100, 10000)) > > return -EBUSY; > > > > + writel(data, priv->ioaddr + mii_data); > > That looks odd. Could you explain why it is needed. > > Thanks > Andrew
Hi Andrew, This mdio c45 support needed to access DWC xPCS which is a Clause-45 MDIO Manageable Device (MMD). This is discuss in: https://patchwork.ozlabs.org/patch/1109776/ https://patchwork.ozlabs.org/patch/1109777/ Since the patch is still WIP to make the xPCS as PHY driver for SGMII to RGMII converter. So i decided to upstream this patch first. Biao Huang also needed this patch and tested pass with this patch on their platform. https://patchwork.ozlabs.org/patch/1103861/ Biao Huang's patch on MDIO-c45 access https://patchwork.ozlabs.org/patch/1092436/ Regards, Weifeng