> > > > > > @@ -155,22 +171,26 @@ static int stmmac_mdio_read(struct
> > > > > > mii_bus *bus,
> > > > > int phyaddr, int phyreg)
> > > > > > struct stmmac_priv *priv = netdev_priv(ndev);
> > > > > > unsigned int mii_address = priv->hw->mii.addr;
> > > > > > unsigned int mii_data = priv->hw->mii.data;
> > > > > > - u32 v;
> > > > > > - int data;
> > > > > > u32 value = MII_BUSY;
> > > > > > + int data = 0;
> > > > > > + u32 v;
> > > > > >
> > > > > > value |= (phyaddr << priv->hw->mii.addr_shift)
> > > > > > & priv->hw->mii.addr_mask;
> > > > > > value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw-
> > > > > >mii.reg_mask;
> > > > > > value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
> > > > > > & priv->hw->mii.clk_csr_mask;
> > > > > > - if (priv->plat->has_gmac4)
> > > > > > + if (priv->plat->has_gmac4) {
> > > > > > value |= MII_GMAC4_READ;
> > > > > > + if (phyreg & MII_ADDR_C45)
> > > > > > + stmmac_mdio_c45_setup(priv, phyreg, &value,
> &data);
> > > > > > + }
> > > > > >
> > > > > > if (readl_poll_timeout(priv->ioaddr + mii_address,
> v, !(v &
> > > > > MII_BUSY),
> > > > > > 100, 10000))
> > > > > > return -EBUSY;
> > > > > >
> > > > > > + writel(data, priv->ioaddr + mii_data);
> > > > >
> > > > > That looks odd. Could you explain why it is needed.
> > > > >
> > > > > Thanks
> > > > > Andrew
> > > >
> > > > Hi Andrew,
> > > > This mdio c45 support needed to access DWC xPCS which is a
> > > > Clause-45
> > >
> > > I mean it looks odd doing a write to the data register in the middle
> > > of stmmac_mdio_read().
> >
> > MAC is using an indirect access to access mdio devices. In order to
> > read, the driver needs to write into both mii_data and mii_address to
> > select c45, read/write command, phy address, address to read, and etc.
>
> Yes, that is all clear. The stmmac_mdio_c45_setup() does part of this
> setup. There is also a write to mii_address which i snipped out when
> replying. But why do you need to write to the data registers during a
> read? C22 does not need this write. Are there some bits in the top of
> the data register which are relevant to C45?
>
Yes, the top 16 bit of the data register only valid when C45 is enable.
It contains the Register address which MDIO c45 frame intended for.
