[PATCHv6 23/28] PCI: mobiveil: Add upper 32-bit CPU base address setup in outbound window

[Hou Zhiqiang]

The current code only setup the lower 32-bit CPU base address in
outbound window, it will result in outbound transactions drop on
64-bit platforms.

Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP driver")
Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
Reviewed-by: Minghuan Lian <minghuan.l...@nxp.com>
Reviewed-by: Subrahmanya Lingappa <l.subrahma...@mobiveil.co.in>
---
V6:
 - Splited from #9 of v5 patches, no functional change.

 drivers/pci/controller/pcie-mobiveil.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/drivers/pci/controller/pcie-mobiveil.c 
b/drivers/pci/controller/pcie-mobiveil.c
index 4f50fe6..9382fed 100644
--- a/drivers/pci/controller/pcie-mobiveil.c
+++ b/drivers/pci/controller/pcie-mobiveil.c
@@ -70,6 +70,7 @@
 
 #define PAB_EXT_AXI_AMAP_SIZE(win)     PAB_EXT_REG_ADDR(0xbaf0, win)
 
+#define PAB_EXT_AXI_AMAP_AXI_WIN(win)  PAB_EXT_REG_ADDR(0x80a0, win)
 #define PAB_AXI_AMAP_AXI_WIN(win)      PAB_REG_ADDR(0x0ba4, win)
 #define  AXI_WINDOW_ALIGN_MASK         3
 
@@ -518,8 +519,10 @@ static void program_ob_windows(struct mobiveil_pcie *pcie, 
int win_num,
         * program AXI window base with appropriate value in
         * PAB_AXI_AMAP_AXI_WIN0 register
         */
-       csr_writel(pcie, cpu_addr & (~AXI_WINDOW_ALIGN_MASK),
+       csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
                   PAB_AXI_AMAP_AXI_WIN(win_num));
+       csr_writel(pcie, upper_32_bits(cpu_addr),
+                  PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
 
        csr_writel(pcie, lower_32_bits(pci_addr),
                   PAB_AXI_AMAP_PEX_WIN_L(win_num));
-- 
1.7.1