On Fri, 5 Jul 2019, Andy Lutomirski wrote: > On Fri, Jul 5, 2019 at 1:36 PM Thomas Gleixner <t...@linutronix.de> wrote: > > No. We can map the APIC into the user space visible page tables for PTI > > without compromising the PTI isolation and it can be read very early on > > before SWAPGS. All you need is a register to clobber not more. It the ISR > > is set, then go into an error path, yell loudly, issue EOI and return. > > The only issue I can see is: It's slow :) > > > I think this will be really extremely slow. If we can restrict this > to x2apic machines, then maybe it's not so awful.
x2apic machines have working iommu/interrupt remapping. > FWIW, if we just patch up the GS thing, then we are still vulnerable: > the bad guy can arrange for a privileged process to have register > state corresponding to a dangerous syscall and then send an int $0x80 > via the APIC. Right, that's why you want to read the APIC:ISR to check where that thing came from. Thanks, tglx