On Fri, 2019-05-10 at 09:24:48 UTC, Christophe Leroy wrote: > Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers > that are summed to obtain the target address. Using 'Z' constraint > and '%y0' argument gives GCC the opportunity to use both registers > instead of only one with the second being forced to 0. > > Suggested-by: Segher Boessenkool <[email protected]> > Signed-off-by: Christophe Leroy <[email protected]>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/6c5875843b87c3adea2beade9d1b8b3d4523900a cheers
