Add an OPP for FSYS APB which reflects the real possible frequency. The bus will have a new parent clock which speed has 600MHz, thus a new possible frequency provided by the clock divider is 150MHz. According to the documentation max possible frequency for this bus is 200MHz.
Signed-off-by: Lukasz Luba <[email protected]> --- arch/arm/boot/dts/exynos5420.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index c7fc4b829b2a..2b36c2f77a10 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -1153,6 +1153,9 @@ opp-hz = /bits/ 64 <100000000>; }; opp01 { + opp-hz = /bits/ 64 <150000000>; + }; + opp02 { opp-hz = /bits/ 64 <200000000>; }; }; -- 2.17.1
