Quoting Codrin Ciubotariu (2019-06-25 02:10:02)
> In clk_generated_determine_rate(), if the divisor is greater than
> GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned.
> If clk_generated_set_rate() will be called later with this wrong
> rate, it will return -EINVAL, so the generated clock won't change
> its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1.
>
> Fixes: 8c7aa6328947 ("clk: at91: clk-generated: remove useless divisor loop")
> Signed-off-by: Codrin Ciubotariu <codrin.ciubota...@microchip.com>
> Acked-by: Nicolas Ferre <nicolas.fe...@microchip.com>
> Acked-by: Ludovic Desroches <ludovic.desroc...@microchip.com>
> ---
Applied to clk-fixes
