Re: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register

[Liang, Kan]

On 7/24/2019 4:29 AM, Yunying Sun wrote:

 From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
counting hardware generated prefetches of L3 cache. But current bitmasks
in driver takes bit 13 as invalid. Here to fix it.

Before:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
  Performance counter stats for 'sleep 3':
    <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

After:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
  Performance counter stats for 'sleep 3':
              9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

Signed-off-by: Yunying Sun <yunying....@intel.com>

Thanks Yunying.

Reviewed-by: Kan Liang <kan.li...@linux.intel.com>

Kan

---
  arch/x86/events/intel/core.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9e911a96972b..b35519cbc8b4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -263,8 +263,8 @@ static struct event_constraint 
intel_icl_event_constraints[] = {
  };

static struct extra_reg intel_icl_extra_regs[] __read_mostly = {

-       INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, 
RSP_0),
-       INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, 
RSP_1),
+       INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, 
RSP_0),
+       INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, 
RSP_1),
        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
        INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
        EVENT_EXTRA_END