[PATCH v6 6/8] KVM: x86: Add CET bits setting in CR4 and XSS

[Yang Weijiang]

CR4.CET(bit 23) is master enable bit for CET feature.
Previously, KVM did not support setting any bits in XSS
so it's hardcoded to check and inject a #GP if Guest
attempted to write a non-zero value to XSS, now it supports
CET related bits setting.

Co-developed-by: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Signed-off-by: Zhang Yi Z <yi.z.zh...@linux.intel.com>
Signed-off-by: Yang Weijiang <weijiang.y...@intel.com>
---
 arch/x86/include/asm/kvm_host.h |  4 +++-
 arch/x86/kvm/cpuid.c            | 11 +++++++++--
 arch/x86/kvm/vmx/vmx.c          |  7 ++-----
 3 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 3731ac37119a..d6c9e44d0115 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -88,7 +88,8 @@
                          | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | 
X86_CR4_PCIDE \
                          | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
                          | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
-                         | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
+                         | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \
+                         | X86_CR4_CET))
 
 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
 
@@ -620,6 +621,7 @@ struct kvm_vcpu_arch {
 
        u64 xcr0;
        u64 guest_supported_xcr0;
+       u64 guest_supported_xss;
        u32 guest_xstate_size;
 
        struct kvm_pio_request pio;
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index d96269a6bcf5..5d740d5a1148 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -119,8 +119,15 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu)
        }
 
        best = kvm_find_cpuid_entry(vcpu, 0xD, 1);
-       if (best && (best->eax & (F(XSAVES) | F(XSAVEC))))
-               best->ebx = xstate_required_size(vcpu->arch.xcr0, true);
+       if (best && (best->eax & (F(XSAVES) | F(XSAVEC)))) {
+               best->ebx = xstate_required_size(vcpu->arch.xcr0 |
+                           kvm_supported_xss(), true);
+
+               vcpu->arch.guest_supported_xss = best->ecx &
+                                                kvm_supported_xss();
+       } else {
+               vcpu->arch.guest_supported_xss = 0;
+       }
 
        /*
         * The existing code assumes virtual address is 48-bit or 57-bit in the
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index fbf9c335cf7b..123285177c6b 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -1940,12 +1940,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct 
msr_data *msr_info)
        case MSR_IA32_XSS:
                if (!vmx_xsaves_supported())
                        return 1;
-               /*
-                * The only supported bit as of Skylake is bit 8, but
-                * it is not supported on KVM.
-                */
-               if (data != 0)
+               if (data & ~vcpu->arch.guest_supported_xss)
                        return 1;
+
                vcpu->arch.ia32_xss = data;
                if (vcpu->arch.ia32_xss != host_xss)
                        add_atomic_switch_msr(vmx, MSR_IA32_XSS,
-- 
2.17.2