The removed barrier isn't needed because the writes/reads are strictly ordered and even if PMC had separate ports for the writes, it wouldn't matter since the hardware logic takes into effect after triggering CPU's power-gating and at that point all CPU accesses are guaranteed to be completed. Hence remove the barrier to eliminate the confusion.
Signed-off-by: Dmitry Osipenko <[email protected]> --- Changelog: v4: No changes. v3: No changes. v2: New patch that was added after Jon's Hunter pointing that it's better not to change the barrier's placement in the code. In fact the barrier is not needed at all. drivers/soc/tegra/pmc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 4e44943d0b26..8f8fb2db064d 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -1460,8 +1460,6 @@ void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) do_div(ticks, USEC_PER_SEC); tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); - wmb(); - value = tegra_pmc_readl(pmc, PMC_CNTRL); value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; value |= PMC_CNTRL_CPU_PWRREQ_OE; -- 2.22.0
