On Tue, 13 Aug 2019, Christoph Hellwig wrote: > This prepare for adding native non-SBI IPI code. > > Signed-off-by: Christoph Hellwig <[email protected]>
Thanks, queued for v5.4-rc1. - Paul
- [PATCH 04/15] riscv: abstract out CSR names for supervis... Christoph Hellwig
- [PATCH 07/15] riscv: read the hart ID from mhartid on bo... Christoph Hellwig
- [PATCH 02/15] riscv: use CSR_SATP instead of the legacy ... Christoph Hellwig
- Re: [PATCH 02/15] riscv: use CSR_SATP instead of th... Paul Walmsley
- Re: [PATCH 02/15] riscv: use CSR_SATP instead o... Christoph Hellwig
- Re: [PATCH 02/15] riscv: use CSR_SATP inste... Paul Walmsley
- Re: [PATCH 02/15] riscv: use CSR_SATP instead of th... Paul Walmsley
- [PATCH 01/15] irqchip/sifive-plic: set max threshold for... Christoph Hellwig
- Re: [PATCH 01/15] irqchip/sifive-plic: set max thre... Paul Walmsley
- [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
- Re: [PATCH 03/15] riscv: refactor the IPI code Paul Walmsley
- [PATCH 08/15] riscv: provide native clint access for M-m... Christoph Hellwig
- [PATCH 15/15] riscv: disable the EFI PECOFF header for M... Christoph Hellwig
- [PATCH 11/15] riscv: don't allow selecting SBI-based dri... Christoph Hellwig
- [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
- [PATCH 09/15] riscv: implement remote sfence.i natively ... Christoph Hellwig
- [PATCH 12/15] riscv: use the correct interrupt levels fo... Christoph Hellwig
- [PATCH 14/15] riscv: add nommu support Christoph Hellwig
- [PATCH 13/15] riscv: clear the instruction cache and all... Christoph Hellwig
