On Fri, Aug 16, 2019 at 11:14:13PM -0700, Stephen Boyd wrote:
> Quoting Niklas Cassel (2019-07-25 03:41:38)
> > + cpr@b018000 {
> > + compatible = "qcom,qcs404-cpr", "qcom,cpr";
> > + reg = <0x0b018000 0x1000>;
> > + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
> > + clocks = <&xo_board>;
> > + clock-names = "ref";
> > + vdd-apc-supply = <&pms405_s3>;
> > + #power-domain-cells = <0>;
> > + operating-points-v2 = <&cpr_opp_table>;
> > + acc-syscon = <&tcsr>;
> > +
> > + nvmem-cells = <&cpr_efuse_quot_offset1>,
> > + <&cpr_efuse_quot_offset2>,
> > + <&cpr_efuse_quot_offset3>,
> > + <&cpr_efuse_init_voltage1>,
> > + <&cpr_efuse_init_voltage2>,
> > + <&cpr_efuse_init_voltage3>,
> > + <&cpr_efuse_quot1>,
> > + <&cpr_efuse_quot2>,
> > + <&cpr_efuse_quot3>,
> > + <&cpr_efuse_ring1>,
> > + <&cpr_efuse_ring2>,
> > + <&cpr_efuse_ring3>,
> > + <&cpr_efuse_revision>;
> > + nvmem-cell-names = "cpr_quotient_offset1",
> > + "cpr_quotient_offset2",
> > + "cpr_quotient_offset3",
> > + "cpr_init_voltage1",
> > + "cpr_init_voltage2",
> > + "cpr_init_voltage3",
> > + "cpr_quotient1",
> > + "cpr_quotient2",
> > + "cpr_quotient3",
> > + "cpr_ring_osc1",
> > + "cpr_ring_osc2",
> > + "cpr_ring_osc3",
> > + "cpr_fuse_revision";
> > +
> > + qcom,cpr-timer-delay-us = <5000>;
> > + qcom,cpr-timer-cons-up = <0>;
> > + qcom,cpr-timer-cons-down = <2>;
> > + qcom,cpr-up-threshold = <1>;
> > + qcom,cpr-down-threshold = <3>;
> > + qcom,cpr-idle-clocks = <15>;
> > + qcom,cpr-gcnt-us = <1>;
> > + qcom,vdd-apc-step-up-limit = <1>;
> > + qcom,vdd-apc-step-down-limit = <1>;
>
> Are any of these qcom,* properties going to change for a particular SoC?
> They look like SoC config data that should just go into the driver and
> change based on the SoC compatible string.
>
Hello Stephen,
thanks a lot for your reviews.
I agree with you, will drop these properties from the dt-binding
and the driver once I respin the series.
I'm hoping to get the cpufreq part of the patch series merged this
merge window, so that the patch pile will decrease.
Kind regards,
Niklas
