On Thu, Sep 05, 2019 at 04:15:47PM +0530, Vidya Sagar wrote: > This patch series enables Tegra194's C5 controller which owns x16 slot in > p2972-0000 platform. C5 controller's PERST# and CLKREQ# are not configured as > output and bi-directional signals by default and hence they need to be > configured explicitly. Also, x16 slot's 3.3V and 12V supplies are controlled > through GPIOs and hence they need to be enabled through regulator framework. > This patch series adds required infrastructural support to address both the > aforementioned requirements. > Testing done on p2972-0000 platform > - Able to enumerate devices connected to x16 slot (owned by C5 controller) > - Enumerated device's functionality verified > - Suspend-Resume sequence is verified with device connected to x16 slot > > V4: > * Rebased (Patch-4/6 particularly) on top of Lorenzo's pci/tegra branch > > V3: > * Addressed some more review comments from Andrew Murray and Thierry Reding > > V2: > * Changed the order of patches in the series for easy merging > * Addressed review comments from Thierry Reding and Andrew Murray > > Vidya Sagar (6): > dt-bindings: PCI: tegra: Add sideband pins configuration entries > dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries > PCI: tegra: Add support to configure sideband pins > PCI: tegra: Add support to enable slot regulators > arm64: tegra: Add configuration for PCIe C5 sideband signals > arm64: tegra: Add PCIe slot supply information in p2972-0000 platform > > .../bindings/pci/nvidia,tegra194-pcie.txt | 16 ++++ > .../arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 24 +++++ > .../boot/dts/nvidia/tegra194-p2972-0000.dts | 4 +- > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++- > drivers/pci/controller/dwc/pcie-tegra194.c | 94 ++++++++++++++++++- > 5 files changed, 172 insertions(+), 4 deletions(-)
Applied to pci/tegra for v5.4, thanks. Lorenzo
