On Fri, Sep 06, 2019 at 01:31:14PM +0000, Jose Abreu wrote:
> From: Voon Weifeng <weifeng.v...@intel.com>
> Date: Sep/05/2019, 13:05:30 (UTC+00:00)
> 
> > DW EQoS v5.xx controllers added capability for interrupt generation
> > when MDIO interface is done (GMII Busy bit is cleared).
> > This patch adds support for this interrupt on supported HW to avoid
> > polling on GMII Busy bit.
> 
> Better leave the enabling of this optional because the support for it is 
> also optional depending on the IP HW configuration.

Hi Jose

If there a register which indicates if this feature is part of the IP?

   Andrew

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