On Mon, 2019-09-09 at 20:19 +0300, Vitaly Gaiduk wrote: > This patch adds ability to switch beetween two PHY SGMII modes. > Some hardware, for example, FPGA IP designs may use 6-wire mode > which enables differential SGMII clock to MAC. > > + > + val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL); > + /* SGMII type is set to 4-wire mode by default. > + * If we place appropriate property in dts (see above) > + * switch on 6-wire mode. > + */ > + if (dp83867->sgmii_ref_clk_en) > + val |= DP83867_SGMII_TYPE; > + else > + val &= ~DP83867_SGMII_TYPE; > + phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
Should use phy_modify_mmd().
