Hi "Ramuthevar,Vadivel, Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master] [cannot apply to v5.3 next-20190915] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Ramuthevar-Vadivel-MuruganX/spi-cadence-qspi-Add-cadence-qspi-support-for-Intel-LGM-SoC/20190916-163033 config: i386-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.4.0-11) 7.4.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 If you fix the issue, kindly add following tag Reported-by: kbuild test robot <l...@intel.com> All warnings (new ones prefixed by >>): drivers/spi/spi-cadence-qspi-apb.c: In function 'cqspi_apb_indirect_write_execute': >> drivers/spi/spi-cadence-qspi-apb.c:382:7: warning: suggest parentheses >> around operand of '!' or change '&' to '&&' or '!' to '~' [-Wparentheses] if (!ret & (*irq_status & CQSPI_IRQ_STATUS_ERR)) { ^~~~ vim +382 drivers/spi/spi-cadence-qspi-apb.c 327 328 static int cqspi_apb_indirect_write_execute(struct struct_cqspi *cadence_qspi, 329 u32 txlen, const u8 *txbuf) 330 { 331 struct platform_device *pdev = cadence_qspi->pdev; 332 struct cqspi_platform_data *pdata = pdev->dev.platform_data; 333 struct cqspi_flash_pdata *f_pdata = 334 &pdata->f_pdata[cadence_qspi->current_cs]; 335 unsigned int *irq_status = &cadence_qspi->irq_status; 336 void __iomem *reg_base = cadence_qspi->iobase; 337 void __iomem *ahb_base = cadence_qspi->qspi_ahb_virt; 338 unsigned int page_size = f_pdata->page_size; 339 int remaining = (int)txlen; 340 u32 write_bytes, timeout, reg; 341 int ret, status = 0; 342 343 writel(0xa, reg_base + CQSPI_REG_INDIRECTTRIGGERADDRRANGE); 344 writel(0x0, reg_base + CQSPI_REG_INDIRECTWRWATERMARK); 345 reg = readl(reg_base + CQSPI_REG_SIZE); 346 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); 347 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); 348 reg |= (f_pdata->page_size << CQSPI_REG_SIZE_PAGE_LSB); 349 reg |= (f_pdata->block_size << CQSPI_REG_SIZE_BLOCK_LSB); 350 writel(reg, reg_base + CQSPI_REG_SIZE); 351 352 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES); 353 writel(CQSPI_REG_SRAM_PARTITION_WR, reg_base + CQSPI_REG_SRAMPARTITION); 354 /* Clear all interrupts. */ 355 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS); 356 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK); 357 writel(CQSPI_REG_INDIRECTWR_START_MASK, 358 reg_base + CQSPI_REG_INDIRECTWR); 359 360 while (remaining > 0) { 361 size_t write_words, mod_bytes; 362 363 write_bytes = remaining > page_size ? page_size : remaining; 364 write_words = write_bytes / 4; 365 mod_bytes = write_bytes % 4; 366 367 if (write_words) { 368 iowrite32_rep(ahb_base, txbuf, write_words); 369 txbuf += (write_words * 4); 370 } 371 if (mod_bytes) { 372 unsigned int temp = 0xFFFFFFFF; 373 374 memcpy(&temp, txbuf, mod_bytes); 375 iowrite32(temp, ahb_base); 376 txbuf += mod_bytes; 377 } 378 ret = wait_event_interruptible_timeout(cadence_qspi->waitqueue, 379 *irq_status & 380 CQSPI_IRQ_MASK_WR, 381 CQSPI_TIMEOUT_MS); > 382 if (!ret & (*irq_status & CQSPI_IRQ_STATUS_ERR)) { 383 ret = -ETIMEDOUT; 384 goto failwr; 385 } else { 386 ret = 0; 387 } 388 remaining -= write_bytes; 389 } 390 391 /* Check indirect done status */ 392 timeout = cadence_qspi_init_timeout(CQSPI_TIMEOUT_MS); 393 while (cadence_qspi_check_timeout(timeout)) { 394 status = readl(reg_base + CQSPI_REG_INDIRECTWR); 395 if (status & CQSPI_REG_INDIRECTWR_DONE_MASK) 396 break; 397 } 398 if (!(status & CQSPI_REG_INDIRECTWR_DONE_MASK)) { 399 ret = -ETIMEDOUT; 400 goto failwr; 401 } 402 return 0; 403 404 failwr: 405 writel(0, reg_base + CQSPI_REG_IRQMASK); 406 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, 407 reg_base + CQSPI_REG_INDIRECTWR); 408 if (ret) 409 writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK, 410 reg_base + CQSPI_REG_INDIRECTWR); 411 return ret; 412 } 413 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
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