On 9/19/19 2:06 AM, David Laight wrote: > From: Tim Chen >> Sent: 18 September 2019 18:16 > ... >> Some users are running machine learning batch tasks with AVX512, and have >> observed >> that these tasks affect the tasks needing a fast response. They have to >> rely on manual CPU affinity to separate these tasks. With appropriate >> latency hint on task, the scheduler can be taught to separate them. > > Will (or can) the scheduler pre-empt a low priority process that is spinning > in userspace in order to allow a high priority (or low latency) process run > on that cpu? > > My suspicion is that the process switch can't happen until (at least) the > next hardware interrupt - and possibly only a timer tick into the scheduler. >
The issue has to do with AVX512 running on the HT sibling, which pulls down the core frequency. So latency sensitive tasks are not blocked but are running concurrently on siblings, but slower. With latency hint, the scheduler can try to avoid putting them on the same core. Tim
