The blsp1_uart3 peripheral appears to be commonly used for interfacing with
other SoCs on a platform, such as a wcn3990 to provide bluetooth.
Signed-off-by: Jeffrey Hugo <jeffrey.l.h...@gmail.com>
---
arch/arm64/boot/dts/qcom/msm8998-pins.dtsi | 13 +++++++++++++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
index 6db70acd38ee..e32d3ab395ea 100644
--- a/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
@@ -75,4 +75,17 @@
drive-strength = <2>; /* 2 mA */
};
};
+
+ blsp1_uart3_on: blsp1_uart3_on {
+ mux {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ function = "blsp_uart3_a";
+ };
+
+ config {
+ pins = "gpio45", "gpio46", "gpio47", "gpio48";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index a3465f6bae84..b69a7f38dd36 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -1214,6 +1214,20 @@
qcom,num-ees = <4>;
};
+ blsp1_uart3: serial@c171000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x0c171000 0x1000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp1_uart3_on>;
+ status = "disabled";
+ };
+
blsp1_i2c1: i2c@c175000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x0c175000 0x600>;
--
2.17.1
