Re: [PATCH V3 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register

[Suzuki K Poulose]

On 05/02/2020 02:33 PM, Anshuman Khandual wrote:

Enable TLB features bit in ID_AA64ISAR0 register as per ARM DDI 0487F.a
specification.

Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <w...@kernel.org>
Cc: Mark Rutland <mark.rutl...@arm.com>
Cc: Suzuki K Poulose <suzuki.poul...@arm.com>
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-kernel@vger.kernel.org

Suggested-by: Will Deacon <w...@kernel.org>
Signed-off-by: Anshuman Khandual <anshuman.khand...@arm.com>
---
  arch/arm64/include/asm/sysreg.h | 1 +
  arch/arm64/kernel/cpufeature.c  | 1 +
  2 files changed, 2 insertions(+)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0f34927f52b9..40eaf89f1032 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -597,6 +597,7 @@

/* id_aa64isar0 */

  #define ID_AA64ISAR0_RNDR_SHIFT               60
+#define ID_AA64ISAR0_TLB_SHIFT         56
  #define ID_AA64ISAR0_TS_SHIFT         52
  #define ID_AA64ISAR0_FHM_SHIFT                48
  #define ID_AA64ISAR0_DP_SHIFT         44
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f4e15e355aee..dbedcae28061 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -174,6 +174,7 @@ static bool __system_matches_cap(unsigned int n);
   */
  static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
        ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 
ID_AA64ISAR0_TLB_SHIFT, 4, 0),

I don't see any reason why this should be VISIBLE to the userspace.

Suzuki