Add the PCI-E root complex reset, correct the pcie-device property, and add the Aspeed SCU interrupt controller include.
Signed-off-by: Eddie James <[email protected]> --- arch/arm/boot/dts/aspeed-g6.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 1ffc1517..86a8e94 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -2,6 +2,7 @@ // Copyright 2019 IBM Corp. #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/aspeed-scu-ic.h> #include <dt-bindings/clock/ast2600-clock.h> / { @@ -342,10 +343,11 @@ compatible = "aspeed,ast2600-xdma"; reg = <0x1e6e7000 0x100>; clocks = <&syscon ASPEED_CLK_GATE_BCLK>; - resets = <&syscon ASPEED_RESET_DEV_XDMA>; + resets = <&syscon ASPEED_RESET_DEV_XDMA>, <&syscon ASPEED_RESET_RC_XDMA>; + reset-names = "device", "root-complex"; interrupts-extended = <&gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <&scu_ic0 2>; - pcie-device = "bmc"; + <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; + aspeed,pcie-device = "bmc"; aspeed,scu = <&syscon>; status = "disabled"; }; -- 1.8.3.1
