[PATCH bpf-next 3/4] bpf, riscv: Optimize BPF_JMP BPF_K when imm == 0 on RV64

[Luke Nelson]

This patch adds an optimization to BPF_JMP (32- and 64-bit) BPF_K for
when the BPF immediate is zero.

When the immediate is zero, the code can directly use the RISC-V zero
register instead of loading a zero immediate to a temporary register
first.

Co-developed-by: Xi Wang <xi.w...@gmail.com>
Signed-off-by: Xi Wang <xi.w...@gmail.com>
Signed-off-by: Luke Nelson <luke.r.n...@gmail.com>
---
 arch/riscv/net/bpf_jit_comp64.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/net/bpf_jit_comp64.c b/arch/riscv/net/bpf_jit_comp64.c
index c3ce9a911b66..b07cef952019 100644
--- a/arch/riscv/net/bpf_jit_comp64.c
+++ b/arch/riscv/net/bpf_jit_comp64.c
@@ -796,7 +796,13 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct 
rv_jit_context *ctx,
        case BPF_JMP32 | BPF_JSET | BPF_K:
                rvoff = rv_offset(i, off, ctx);
                s = ctx->ninsns;
-               emit_imm(RV_REG_T1, imm, ctx);
+               if (imm) {
+                       emit_imm(RV_REG_T1, imm, ctx);
+                       rs = RV_REG_T1;
+               } else {
+                       /* If imm is 0, simply use zero register. */
+                       rs = RV_REG_ZERO;
+               }
                if (!is64) {
                        if (is_signed_bpf_cond(BPF_OP(code)))
                                emit_sext_32_rd(&rd, ctx);
@@ -811,11 +817,10 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct 
rv_jit_context *ctx,
                if (BPF_OP(code) == BPF_JSET) {
                        /* Adjust for and */
                        rvoff -= 4;
-                       emit(rv_and(RV_REG_T1, rd, RV_REG_T1), ctx);
-                       emit_branch(BPF_JNE, RV_REG_T1, RV_REG_ZERO, rvoff,
-                                   ctx);
+                       emit(rv_and(rs, rd, rs), ctx);
+                       emit_branch(BPF_JNE, rs, RV_REG_ZERO, rvoff, ctx);
                } else {
-                       emit_branch(BPF_OP(code), rd, RV_REG_T1, rvoff, ctx);
+                       emit_branch(BPF_OP(code), rd, rs, rvoff, ctx);
                }
                break;
 
-- 
2.17.1