On Wed, 2020-05-06 at 23:00 +0200, Enric Balletbo i Serra wrote: > Hi Weiyi, > > Thank you for your patch. > > On 6/5/20 10:15, Weiyi Lu wrote: > > The functions provided by infracfg misc driver have no other user except > > the scpsys driver so move those into scpsys driver directly. > > And then, remove infracfg misc drvier which is no longer being used. > > Typo: s/drvier/driver/
I'll fix it, thank you. > > > BTW, in next patch, we're going to extend the bus protection functions > > with more customized arguments. > > > > Signed-off-by: Weiyi Lu <[email protected]> > > Reviewed-by: Enric Balletbo i Serra <[email protected]> > Thanks for your reviewing. > > --- > > drivers/soc/mediatek/Kconfig | 10 ----- > > drivers/soc/mediatek/Makefile | 1 - > > drivers/soc/mediatek/mtk-infracfg.c | 79 > > ----------------------------------- > > drivers/soc/mediatek/mtk-scpsys.c | 66 +++++++++++++++++++++++++---- > > include/linux/soc/mediatek/infracfg.h | 39 ----------------- > > 5 files changed, 57 insertions(+), 138 deletions(-) > > delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c > > delete mode 100644 include/linux/soc/mediatek/infracfg.h > > > > diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig > > index 2114b56..f837b3c 100644 > > --- a/drivers/soc/mediatek/Kconfig > > +++ b/drivers/soc/mediatek/Kconfig > > @@ -10,21 +10,12 @@ config MTK_CMDQ > > depends on ARCH_MEDIATEK || COMPILE_TEST > > select MAILBOX > > select MTK_CMDQ_MBOX > > - select MTK_INFRACFG > > help > > Say yes here to add support for the MediaTek Command Queue (CMDQ) > > driver. The CMDQ is used to help read/write registers with critical > > time limitation, such as updating display configuration during the > > vblank. > > > > -config MTK_INFRACFG > > - bool "MediaTek INFRACFG Support" > > - select REGMAP > > - help > > - Say yes here to add support for the MediaTek INFRACFG controller. The > > - INFRACFG controller contains various infrastructure registers not > > - directly associated to any device. > > - > > config MTK_PMIC_WRAP > > tristate "MediaTek PMIC Wrapper Support" > > depends on RESET_CONTROLLER > > @@ -38,7 +29,6 @@ config MTK_SCPSYS > > bool "MediaTek SCPSYS Support" > > default ARCH_MEDIATEK > > select REGMAP > > - select MTK_INFRACFG > > select PM_GENERIC_DOMAINS if PM > > help > > Say yes here to add support for the MediaTek SCPSYS power domain > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > > index b017330..2b2c2537 100644 > > --- a/drivers/soc/mediatek/Makefile > > +++ b/drivers/soc/mediatek/Makefile > > @@ -1,5 +1,4 @@ > > # SPDX-License-Identifier: GPL-2.0-only > > obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o > > -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > > diff --git a/drivers/soc/mediatek/mtk-infracfg.c > > b/drivers/soc/mediatek/mtk-infracfg.c > > deleted file mode 100644 > > index 341c7ac..0000000 > > --- a/drivers/soc/mediatek/mtk-infracfg.c > > +++ /dev/null > > @@ -1,79 +0,0 @@ > > -// SPDX-License-Identifier: GPL-2.0-only > > -/* > > - * Copyright (c) 2015 Pengutronix, Sascha Hauer <[email protected]> > > - */ > > - > > -#include <linux/export.h> > > -#include <linux/jiffies.h> > > -#include <linux/regmap.h> > > -#include <linux/soc/mediatek/infracfg.h> > > -#include <asm/processor.h> > > - > > -#define MTK_POLL_DELAY_US 10 > > -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) > > - > > -#define INFRA_TOPAXI_PROTECTEN 0x0220 > > -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > - > > -/** > > - * mtk_infracfg_set_bus_protection - enable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be enabled. > > - * @reg_update: The boolean flag determines to set the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with set register(PROTECTEN_SET). > > - * > > - * This function enables the bus protection bits for disabled power > > - * domains so that the system does not hang when some unit accesses the > > - * bus while in power down. > > - */ > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - u32 val; > > - int ret; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > - mask); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, (val & mask) == mask, > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > - > > -/** > > - * mtk_infracfg_clear_bus_protection - disable bus protection > > - * @regmap: The infracfg regmap > > - * @mask: The mask containing the protection bits to be disabled. > > - * @reg_update: The boolean flag determines to clear the protection bits > > - * by regmap_update_bits with enable register(PROTECTEN) or > > - * by regmap_write with clear register(PROTECTEN_CLR). > > - * > > - * This function disables the bus protection bits previously enabled with > > - * mtk_infracfg_set_bus_protection. > > - */ > > - > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update) > > -{ > > - int ret; > > - u32 val; > > - > > - if (reg_update) > > - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > - else > > - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > - > > - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > - val, !(val & mask), > > - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > - > > - return ret; > > -} > > diff --git a/drivers/soc/mediatek/mtk-scpsys.c > > b/drivers/soc/mediatek/mtk-scpsys.c > > index c9c3cf7..b603af7 100644 > > --- a/drivers/soc/mediatek/mtk-scpsys.c > > +++ b/drivers/soc/mediatek/mtk-scpsys.c > > @@ -10,8 +10,8 @@ > > #include <linux/of_device.h> > > #include <linux/platform_device.h> > > #include <linux/pm_domain.h> > > +#include <linux/regmap.h> > > #include <linux/regulator/consumer.h> > > -#include <linux/soc/mediatek/infracfg.h> > > > > #include <dt-bindings/power/mt2701-power.h> > > #include <dt-bindings/power/mt2712-power.h> > > @@ -78,6 +78,29 @@ > > #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ > > #define PWR_STATUS_WB BIT(27) /* MT7622 */ > > > > +#define INFRA_TOPAXI_PROTECTEN 0x0220 > > +#define INFRA_TOPAXI_PROTECTSTA1 0x0228 > > +#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 > > +#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 > > + > > +#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > +#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > + > > +#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > +#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > + BIT(28)) > > +#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > + BIT(7) | BIT(8)) > > + > > +#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > +#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > +#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > + > > #define MAX_CLKS 3 > > > > /** > > @@ -251,25 +274,50 @@ static int scpsys_sram_disable(struct scp_domain > > *scpd, void __iomem *ctl_addr) > > static int scpsys_bus_protect_enable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_set_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, > > + mask); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, (val & mask) == mask, > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_bus_protect_disable(struct scp_domain *scpd) > > { > > struct scp *scp = scpd->scp; > > + struct regmap *infracfg = scp->infracfg; > > + u32 mask = scpd->data->bus_prot_mask; > > + bool reg_update = scp->bus_prot_reg_update; > > + u32 val; > > + int ret; > > > > - if (!scpd->data->bus_prot_mask) > > + if (!mask) > > return 0; > > > > - return mtk_infracfg_clear_bus_protection(scp->infracfg, > > - scpd->data->bus_prot_mask, > > - scp->bus_prot_reg_update); > > + if (reg_update) > > + regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); > > + else > > + regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); > > + > > + ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, > > + val, !(val & mask), > > + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); > > + > > + return ret; > > } > > > > static int scpsys_power_on(struct generic_pm_domain *genpd) > > diff --git a/include/linux/soc/mediatek/infracfg.h > > b/include/linux/soc/mediatek/infracfg.h > > deleted file mode 100644 > > index fd25f01..0000000 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ /dev/null > > @@ -1,39 +0,0 @@ > > -/* SPDX-License-Identifier: GPL-2.0 */ > > -#ifndef __SOC_MEDIATEK_INFRACFG_H > > -#define __SOC_MEDIATEK_INFRACFG_H > > - > > -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) > > -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) > > -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) > > -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) > > -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) > > -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) > > -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) > > -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) > > -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) > > -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) > > -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) > > - > > -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) > > -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) > > - > > -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) > > -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ > > - BIT(28)) > > -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ > > - BIT(7) | BIT(8)) > > - > > -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, > > - bool reg_update); > > -#endif /* __SOC_MEDIATEK_INFRACFG_H */ > >
