> -----Original Message----- > From: Felipe Balbi <[email protected]> On Behalf Of Felipe Balbi > Sent: 2020年5月16日 19:57 > To: Jun Li <[email protected]>; Thinh Nguyen <[email protected]>; Jun Li > <[email protected]> > Cc: John Stultz <[email protected]>; lkml > <[email protected]>; Yu > Chen <[email protected]>; Greg Kroah-Hartman <[email protected]>; > Rob > Herring <[email protected]>; Mark Rutland <[email protected]>; ShuFan Lee > <[email protected]>; Heikki Krogerus <[email protected]>; > Suzuki K Poulose <[email protected]>; Chunfeng Yun > <[email protected]>; Hans de Goede <[email protected]>; Andy > Shevchenko > <[email protected]>; Valentin Schneider <[email protected]>; > Jack Pham <[email protected]>; Linux USB List <[email protected]>; > open > list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS > <[email protected]>; > Peter Chen <[email protected]>; Thinh Nguyen <[email protected]> > Subject: RE: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by > device > controller > > > Hi, > > Jun Li <[email protected]> writes: > >> >> Hi Thinh, could you comment this? > >> > > >> > You only need to wake up the usb2 phy when issuing the command > >> > while running in highspeed or below. If you're running in SS or > >> > higher, internally the controller does it for you for usb3 phy. In > >> > Jun's case, it seems like it takes longer for his phy to wake up. > >> > > >> > IMO, in this case, I think it's fine to increase the command timeout. > >> > >> Is there an upper limit to this? Is 32k clock the slowest that can be > >> fed to the PHY as a suspend clock? > > > > Yes, 32K clock is the slowest, Per DWC3 document on Power Down Scale > > (bits 31:19 of GCTL): > > > > "Power Down Scale (PwrDnScale) > > The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to > > a small part of the USB3 controller that operates when the SS PHY is > > in its lowest power (P3) state, and therefore does not provide a clock. > > The Power Down Scale field specifies how many suspend_clk periods fit > > into a 16 kHz clock period. When performing the division, round up the > > remainder. > > For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend > > clock, Power Down Scale = 25000 kHz/16 kHz = 13'd1563 (rounder up) > > Note: > > - Minimum Suspend clock frequency is 32 kHz > > - Maximum Suspend clock frequency is 125 MHz" > > Cool, now do we have an upper bound for how many clock cycles it takes to > wake up > the PHY? My understanding is this ep command does not wake up the SS PHY, the SS PHY still stays at P3 when execute this ep command. The time required here is to wait controller complete something for this ep command with 32K clock.
> Then we can just set the time to that upper bound. Per my test with trace, the time is about 400us(~13 cycles). Thanks Li Jun > > -- > balbi
