On Tue, May 19, 2020 at 05:42:13PM +0200, Thomas Bogendoerfer wrote: > On Wed, May 06, 2020 at 08:42:30PM +0300, sergey.se...@baikalelectronics.ru > wrote: > > From: Serge Semin <sergey.se...@baikalelectronics.ru> > > > > When XPA mode is enabled the normally 32-bits MAAR pair registers > > are extended to be of 64-bits width as in pure 64-bits MIPS > > architecture. In this case the MAAR registers can enable the > > speculative loads/stores for addresses of up to 39-bits width. > > But in this case the process of the MAAR initialization changes a bit. > > The upper 32-bits of the registers are supposed to be accessed by mean > > of the dedicated instructions mfhc0/mthc0 and there is a CP0.MAAR.VH > > bit which should be set together with CP0.MAAR.VL as indication > > of the boundary validity. All of these peculiarities were taken into > > account in this commit so the speculative loads/stores would work > > when XPA mode is enabled. > > > > Co-developed-by: Alexey Malahov <alexey.mala...@baikalelectronics.ru> > > Signed-off-by: Alexey Malahov <alexey.mala...@baikalelectronics.ru> > > Signed-off-by: Serge Semin <sergey.se...@baikalelectronics.ru> > > Cc: Thomas Bogendoerfer <tsbog...@alpha.franken.de> > > Cc: Paul Burton <paulbur...@kernel.org> > > Cc: Ralf Baechle <r...@linux-mips.org> > > Cc: Arnd Bergmann <a...@arndb.de> > > Cc: Rob Herring <robh...@kernel.org> > > Cc: linux...@vger.kernel.org > > Cc: devicet...@vger.kernel.org > > --- > > arch/mips/include/asm/maar.h | 17 +++++++++++++++-- > > arch/mips/include/asm/mipsregs.h | 10 ++++++++++ > > arch/mips/mm/init.c | 8 +++++++- > > 3 files changed, 32 insertions(+), 3 deletions(-) > > applied to mips-next.
Great! Thanks. -Sergey > > Thomas. > > -- > Crap can work. Given enough thrust pigs will fly, but it's not necessarily a > good idea. [ RFC1925, 2.3 ]
