On 2020-05-20 14:19, Bart Van Assche wrote: > On 2020-05-20 10:55, Christoph Hellwig wrote: >> HPB is a completely fucked up concept and we shoud not merge it at all. >> Especially not with a crazy bullshit vendor extension layer that makes >> it even easier for vendors to implement even worse things than the >> already horrible spec says. Just stop this crap and implement sane >> interfaces for the next generation hardware instead of wasting your >> time on this idiotic idea. > > What exactly is it that you are not happy about? Is it the concept of > using host memory to store L2P translation information or how that > concept has been translated into SCSI commands (HPB READ BUFFER, HPB > READ and HPB WRITE BUFFER)? > > In the former case: aren't Open-Channel SSDs another example of storage > devices for which the L2P translation tables are maintained in host > memory? Didn't the driver for Fusion-io SSDs also maintain the L2P > mapping in host memory? > > Do you agree that HPB UFS storage devices are already being used widely > and hence that not accepting this functionality in the upstream kernel > will force users of HPB devices to maintain HPB code outside the kernel > tree? Isn't one of the goals of the Linux kernel project to increase its > user base?
The following quote from https://www.anandtech.com/show/13474/the-google-pixel-3-review/2 is interesting: "Another big improvement for file I/O is the implementation of “Host Performance Booster” in the kernel and UFS controller firmware stack. HPB is essentially caching of the NAND chip’s FTL (flash translation layer) L2P (logical to physical) mapping tables into the hosts (SoCs) main memory. This allows the host driver to look up the target L2P entry directly without betting on UFS’s limited SRAM to have a cache-hit, reducing latency and greatly increasing random read performance. The authors of the feature showcase an improvement of 59-67% in random I/O read performance due to the new feature. It’s worth to mention that traditional Android I/O benchmarks won’t be able to show this as as those tend to test read speeds with the files they’ve just created." Given the cost of SRAM in embedded controllers I think there is a strong incentive for manufacturers of flash storage devices to reduce the amount of SRAM on the storage controller. I think this means that proposals to use host memory for caching L2P mappings will keep popping up, no matter what we tell the storage controller vendors about what we think about such a design. Bart.
