On Tue, May 26, 2020 at 10:09:15AM -0600, Rob Herring wrote: > On Tue, 26 May 2020 15:59:25 +0300, Serge Semin wrote: > > There is a single register provided by the SoC system controller, > > which can be used to tune the L2-cache RAM up. It only provides a way > > to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" > > compatible string the device node can be optionally equipped with the > > properties of Tag/Data/WS latencies. > > > > Signed-off-by: Serge Semin <[email protected]> > > Cc: Alexey Malahov <[email protected]> > > Cc: Paul Burton <[email protected]> > > Cc: Olof Johansson <[email protected]> > > Cc: [email protected] > > Cc: [email protected] > > > > --- > > > > Changelog v2: > > - Move driver to the memory subsystem. > > - Use dual GPL/BSD license. > > - Use single lined copyright header. > > - Move "allOf" restrictions to the root level of the properties. > > - Discard syscon compatible string and reg property. > > - The DT node is supposed to be a child of the Baikal-T1 system controller > > node. > > > > Changelog v3: > > - Get the reg property back even though the driver is using the parental > > syscon regmap. > > - The DT schema will live separately from the system controller, but the > > corresponding sub-node of the later DT schema will $ref this one. > > - Set non-default latencies in the example. > > --- > > .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 +++++++++++++++++++ > > 1 file changed, 63 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > > > > Reviewed-by: Rob Herring <[email protected]>
Great! Thanks. -Sergey
