Hi Mylène,
Am Montag, 1. Juni 2020, 17:14:42 CEST schrieb Mylène Josserand:
> The revision rk3288w has a different clock tree about "hclk_vio"
> clock, according to the BSP kernel code.
>
> This patch handles this difference by detecting which device-tree
> we are using. If it is a "rockchip,rk3288-cru", let's register
> the clock tree as it was before. If the compatible is
> "rockchip,rk3288w-cru", we will apply the difference according to this
> version of this SoC.
>
> Noticed that this new device-tree compatible must be handled by
> bootloader.
>
> Signed-off-by: Mylène Josserand <mylene.josser...@collabora.com>
approach looks good, but you should also update the clock-controller
dt-binding for the new compatible.
Style nits below.
> ---
> drivers/clk/rockchip/clk-rk3288.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3288.c
> b/drivers/clk/rockchip/clk-rk3288.c
> index cc2a177bbdbf..5018d2f1e54c 100644
> --- a/drivers/clk/rockchip/clk-rk3288.c
> +++ b/drivers/clk/rockchip/clk-rk3288.c
> @@ -425,8 +425,6 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = {
> COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p,
> CLK_IGNORE_UNUSED,
> RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 0, GFLAGS),
> - DIV(0, "hclk_vio", "aclk_vio0", 0,
> - RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
> COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p,
> CLK_IGNORE_UNUSED,
> RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK3288_CLKGATE_CON(3), 2, GFLAGS),
> @@ -819,6 +817,16 @@ static struct rockchip_clk_branch rk3288_clk_branches[]
> __initdata = {
> INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3,
> IFLAGS),
> };
>
> +static struct rockchip_clk_branch rk3288w_hclkvio_branch[] __initdata = {
> + DIV(0, "hclk_vio", "aclk_vio1", 0,
> + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
please keep indentations as they were, the sub-lines starting where they
are is actually intentional :-)
> +};
> +
> +static struct rockchip_clk_branch rk3288_hclkvio_branch[] __initdata = {
> + DIV(0, "hclk_vio", "aclk_vio0", 0,
> + RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
same here
> +};
> +
> static const char *const rk3288_critical_clocks[] __initconst = {
> "aclk_cpu",
> "aclk_peri",
> @@ -936,6 +944,14 @@ static void __init rk3288_clk_init(struct device_node
> *np)
> RK3288_GRF_SOC_STATUS1);
> rockchip_clk_register_branches(ctx, rk3288_clk_branches,
> ARRAY_SIZE(rk3288_clk_branches));
> +
> + if (of_device_is_compatible(np, "rockchip,rk3288w-cru"))
> + rockchip_clk_register_branches(ctx, rk3288w_hclkvio_branch,
> +
> ARRAY_SIZE(rk3288w_hclkvio_branch));
> + else
> + rockchip_clk_register_branches(ctx, rk3288_hclkvio_branch,
> +
> ARRAY_SIZE(rk3288_hclkvio_branch));
> +
> rockchip_clk_protect_critical(rk3288_critical_clocks,
> ARRAY_SIZE(rk3288_critical_clocks));
>
>
