[PATCH v2] ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add device tree for camera DB

[Lad Prabhakar]

Add support for the camera daughter board which is connected to
iWave's RZ/G1H Qseven carrier board. Also enable ttySC[0135] and
ethernet1 interfaces.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad...@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu...@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+rene...@glider.be>
---
v1->v2
* Enabled support for RTS/CTS for SCIFB1 interface through gpio pins
* Included Reviewed-by tag from Geert 
---
 arch/arm/boot/dts/Makefile                      |  1 +
 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts | 97 +++++++++++++++++++++++++
 2 files changed, 98 insertions(+)
 create mode 100644 arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ed3376c..118e35c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -918,6 +918,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
        r8a73a4-ape6evm.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7742-iwg21d-q7.dtb \
+       r8a7742-iwg21d-q7-dbcm-ca.dtb \
        r8a7743-iwg20d-q7.dtb \
        r8a7743-iwg20d-q7-dbcm-ca.dtb \
        r8a7743-sk-rzg1m.dtb \
diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts 
b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
new file mode 100644
index 0000000..1479ced
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1H Qseven board development
+ * platform with camera daughter board
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7742-iwg21d-q7.dts"
+
+/ {
+       model = "iWave Systems RZ/G1H Qseven development platform with camera 
add-on";
+       compatible = "iwave,g21d", "iwave,g21m", "renesas,r8a7742";
+
+       aliases {
+               serial0 = &scif0;
+               serial1 = &scif1;
+               serial3 = &scifb1;
+               serial5 = &hscif0;
+               ethernet1 = &ether;
+       };
+};
+
+&avb {
+       /* Pins shared with VIN0, keep status disabled */
+       status = "disabled";
+};
+
+&ether {
+       pinctrl-0 = <&ether_pins>;
+       pinctrl-names = "default";
+
+       phy-handle = <&phy1>;
+       renesas,ether-link-active-low;
+       status = "okay";
+
+       phy1: ethernet-phy@1 {
+               reg = <1>;
+               micrel,led-mode = <1>;
+       };
+};
+
+&hscif0 {
+       pinctrl-0 = <&hscif0_pins>;
+       pinctrl-names = "default";
+       uart-has-rtscts;
+       status = "okay";
+};
+
+&pfc {
+       ether_pins: ether {
+               groups = "eth_mdio", "eth_rmii";
+               function = "eth";
+       };
+
+       hscif0_pins: hscif0 {
+               groups = "hscif0_data", "hscif0_ctrl";
+               function = "hscif0";
+       };
+
+       scif0_pins: scif0 {
+               groups = "scif0_data";
+               function = "scif0";
+       };
+
+       scif1_pins: scif1 {
+               groups = "scif1_data";
+               function = "scif1";
+       };
+
+       scifb1_pins: scifb1 {
+               groups = "scifb1_data";
+               function = "scifb1";
+       };
+};
+
+&scif0 {
+       pinctrl-0 = <&scif0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&scif1 {
+       pinctrl-0 = <&scif1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&scifb1 {
+       pinctrl-0 = <&scifb1_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       rts-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+       cts-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+};
-- 
2.7.4