> Am 27.06.2020 um 15:55 schrieb Drew Fustini <d...@beagleboard.org>:
>
> These pins on the PocketBeagle P1 and P2 headers are connected to AM3358
> balls with gpio lines, and these pins are not used for any other
> peripherals by default. These GPIO lines are unclaimed and could be used
> by userspace program through the gpiod ABI. However, no driver will have
> set mux mode for the pins.
>
> This patch adds a "default" state in the am33xx_pinmux node and sets the
> pins to gpio output mux mode.
wouldn't it be more safe to set them to input mode?
BR,
Nikolaus Schaller
>
> Signed-off-by: Drew Fustini <d...@beagleboard.org>
> ---
> arch/arm/boot/dts/am335x-pocketbeagle.dts | 98 +++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm/boot/dts/am335x-pocketbeagle.dts
> b/arch/arm/boot/dts/am335x-pocketbeagle.dts
> index f0b222201b86..900dc6558701 100644
> --- a/arch/arm/boot/dts/am335x-pocketbeagle.dts
> +++ b/arch/arm/boot/dts/am335x-pocketbeagle.dts
> @@ -60,6 +60,104 @@ vmmcsd_fixed: fixedregulator0 {
> };
>
> &am33xx_pinmux {
> +
> + pinctrl-names = "default";
> + pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio
> + &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio
> + &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio
> + &P2_17_gpio >;
> +
> + /* P2_03 (ZCZ ball T10) gpio0_23 0x824 */
> + P2_03_gpio: pinmux_P2_03_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P1_34 (ZCZ ball T11) gpio0_26 0x828 */
> + P1_34_gpio: pinmux_P1_34_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_19 (ZCZ ball U12) gpio0_27 0x82c */
> + P2_19_gpio: pinmux_P2_19_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_24 (ZCZ ball T12) gpio1_12 0x830 */
> + P2_24_gpio: pinmux_P2_24_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_33 (ZCZ ball R12) gpio1_13 0x834 */
> + P2_33_gpio: pinmux_P2_33_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_22 (ZCZ ball V13) gpio1_14 0x838 */
> + P2_22_gpio: pinmux_P2_22_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_18 (ZCZ ball U13) gpio1_15 0x83c */
> + P2_18_gpio: pinmux_P2_18_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_10 (ZCZ ball R14) gpio1_20 0x850 */
> + P2_10_gpio: pinmux_P2_10_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_06 (ZCZ ball U16) gpio1_25 0x864 */
> + P2_06_gpio: pinmux_P2_06_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_04 (ZCZ ball T16) gpio1_26 0x868 */
> + P2_04_gpio: pinmux_P2_04_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_02 (ZCZ ball V17) gpio1_27 0x86c */
> + P2_02_gpio: pinmux_P2_02_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_08 (ZCZ ball U18) gpio1_28 0x878 */
> + P2_08_gpio: pinmux_P2_08_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> + /* P2_17 (ZCZ ball V12) gpio2_1 0x88c */
> + P2_17_gpio: pinmux_P2_17_gpio {
> + pinctrl-single,pins = <
> + AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_OUTPUT,
> MUX_MODE7)
> + >;
> + };
> +
> i2c2_pins: pinmux-i2c2-pins {
> pinctrl-single,pins = <
> AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP,
> MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */
> --
> 2.25.1
>
