On Thu, Jul 09, 2020 at 04:00:48PM -0700, Dave Hansen wrote: > On 7/8/20 2:51 AM, tip-bot2 for Kan Liang wrote: > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index 02dabc9..72ba4c5 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -366,6 +366,7 @@ > > #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU > > buffers */ > > #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" > > TSX_FORCE_ABORT */ > > #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ > > +#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ > > #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation > > Control (IBRS + IBPB) */ > > #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread > > Indirect Branch Predictors */ > > #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ > > Are architectural LBRs useful *without* XSAVE? If not, should we add an > entry in arch/x86/kernel/cpu/cpuid-deps.c::cpuid_deps[] for this?
Yes, look at patch 22, without the XSAVE thing it'll fall back to poking at MSRs lots.
