On 15/07/2020 14:24:11+0300, Claudiu Beznea wrote:
> According to datasheet mul mask is on bits 31..24.
>
> Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
> Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.bell...@bootlin.com>
> ---
> drivers/clk/at91/clk-sam9x60-pll.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
> b/drivers/clk/at91/clk-sam9x60-pll.c
> index e699803986e5..3522eae2edd6 100644
> --- a/drivers/clk/at91/clk-sam9x60-pll.c
> +++ b/drivers/clk/at91/clk-sam9x60-pll.c
> @@ -15,7 +15,7 @@
> #include "pmc.h"
>
> #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
> -#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
> +#define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
>
> #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
> #define UPLL_DIV 2
> --
> 2.7.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
