On 15/07/2020 14:24:10+0300, Claudiu Beznea wrote:
> Check best_rate against available clock ranges.
>
> Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
> Signed-off-by: Claudiu Beznea <claudiu.bez...@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.bell...@bootlin.com>
> ---
> drivers/clk/at91/clk-generated.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/at91/clk-generated.c
> b/drivers/clk/at91/clk-generated.c
> index 995a13133cfb..f8e557e0e1b8 100644
> --- a/drivers/clk/at91/clk-generated.c
> +++ b/drivers/clk/at91/clk-generated.c
> @@ -185,8 +185,8 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
> __clk_get_name((req->best_parent_hw)->clk),
> req->best_parent_rate);
>
> - if (best_rate < 0)
> - return best_rate;
> + if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
> + return -EINVAL;
>
> req->rate = best_rate;
> return 0;
> --
> 2.7.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
