On failure pcie_capability_read_dword() sets it's last parameter,
val to 0. In this case dn and up will be 0, so aspm_hw_l1_supported()
will return false.
However, with Patch 12/12, it is possible that val is set to ~0 on
failure. This would introduce a bug because (x & x) == (~0 & x). So
with dn and up being 0x02, a true value is return when the read has
actually failed.
Since, the value ~0 is invalid here,
Reset dn and up to 0 when a value of ~0 is read into them, this
ensures false is returned on failure in this case.
Suggested-by: Bjorn Helgaas <bj...@helgaas.com>
Signed-off-by: Saheed O. Bolarinwa <refactormys...@gmail.com>
---
drivers/infiniband/hw/hfi1/aspm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/infiniband/hw/hfi1/aspm.c
b/drivers/infiniband/hw/hfi1/aspm.c
index a3c53be4072c..9605b2145d19 100644
--- a/drivers/infiniband/hw/hfi1/aspm.c
+++ b/drivers/infiniband/hw/hfi1/aspm.c
@@ -33,13 +33,13 @@ static bool aspm_hw_l1_supported(struct hfi1_devdata *dd)
return false;
pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &dn);
- dn = ASPM_L1_SUPPORTED(dn);
+ dn = (dn == (u32)~0) ? 0 : ASPM_L1_SUPPORTED(dn);
pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &up);
- up = ASPM_L1_SUPPORTED(up);
+ up = (up == (u32)~0) ? 0 : ASPM_L1_SUPPORTED(up);
/* ASPM works on A-step but is reported as not supported */
- return (!!dn || is_ax(dd)) && !!up;
+ return (dn || is_ax(dd)) && up;
}
/* Set L1 entrance latency for slower entry to L1 */
--
2.18.4
