[PATCH 07/16] arm64: dts: imx8mm-evk: Align pin configuration group names with schema

[Krzysztof Kozlowski]

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts 
b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 0115f07bbc9d..207dc8de3145 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -423,13 +423,13 @@
                >;
        };
 
-       pinctrl_pmic: pmicirq {
+       pinctrl_pmic: pmicirqgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x41
                >;
        };
 
-       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
                >;
@@ -457,7 +457,7 @@
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
                >;
@@ -475,7 +475,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
@@ -487,7 +487,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
@@ -515,7 +515,7 @@
                >;
        };
 
-       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
                        MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
@@ -531,7 +531,7 @@
                >;
        };
 
-       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
                        MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
-- 
2.17.1