[PATCH 16/16] arm64: dts: imx8qxp-colibri: Align pin configuration group names with schema

[Krzysztof Kozlowski]

Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:

    ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>
---
 arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 75f17a29f81e..f38acff0d25c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -494,7 +494,7 @@
                >;
        };
 
-       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                fsl,pins = <
                        IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                
0x06000041
                        IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                0x21
@@ -511,7 +511,7 @@
                >;
        };
 
-       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                fsl,pins = <
                        IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                
0x06000041
                        IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                0x21
@@ -554,7 +554,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK              
0x06000041      /* SODIMM  47 */
                        IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD              0x21    
        /* SODIMM 190 */
@@ -566,7 +566,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK              
0x06000041      /* SODIMM  47 */
                        IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD              0x21    
        /* SODIMM 190 */
-- 
2.17.1