On Mon, Aug 24, 2020 at 10:54:22AM +0200, Joerg Roedel wrote: > From: Tom Lendacky <thomas.lenda...@amd.com> > > Handle #VC exceptions caused by CPUID instructions. These happen in > early boot code when the KASLR code checks for RDTSC. > > Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com> > [ jroe...@suse.de: Adapt to #VC handling framework ] > Co-developed-by: Joerg Roedel <jroe...@suse.de> > Signed-off-by: Joerg Roedel <jroe...@suse.de> > Link: https://lore.kernel.org/r/20200724160336.5435-27-j...@8bytes.org > --- > + > +static enum es_result vc_handle_cpuid(struct ghcb *ghcb, > + struct es_em_ctxt *ctxt) > +{ > + struct pt_regs *regs = ctxt->regs; > + u32 cr4 = native_read_cr4(); > + enum es_result ret; > + > + ghcb_set_rax(ghcb, regs->ax); > + ghcb_set_rcx(ghcb, regs->cx); > + > + if (cr4 & X86_CR4_OSXSAVE)
Will this ever happen? trampoline_32bit_src will clear CR4 except for PAE and possibly LA57, no? > + /* Safe to read xcr0 */ > + ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK)); > + else > + /* xgetbv will cause #GP - use reset value for xcr0 */ > + ghcb_set_xcr0(ghcb, 1); > + > + ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0); > + if (ret != ES_OK) > + return ret; > + > + if (!(ghcb_rax_is_valid(ghcb) && > + ghcb_rbx_is_valid(ghcb) && > + ghcb_rcx_is_valid(ghcb) && > + ghcb_rdx_is_valid(ghcb))) > + return ES_VMM_ERROR; > + > + regs->ax = ghcb->save.rax; > + regs->bx = ghcb->save.rbx; > + regs->cx = ghcb->save.rcx; > + regs->dx = ghcb->save.rdx; > + > + return ES_OK; > +} > -- > 2.28.0 >
