Quoting Jonathan Marek (2020-09-03 13:43:10) > On 9/2/20 7:02 PM, Stephen Boyd wrote: > > > > This code is based on a submission of this phy and PLL in the drm > > subsystem. > > I updated my upstream-based sm8150/sm8250 displayport stack [1] to use > these patches.
Great! > > This commit [2] might interest you, so that you can consider what needs > to change between v3 and v4 PHYs. Note some of the V4 registers have the > same address as V3, so the diff could be smaller. Looks like v4 will need to introduce a register indirection table for the differences. Also need to add a table for the aux initial table values and the calibration values for aux_cfg1. Seems like it won't be too bad. Does DP work with those patches with v4? You should make yourself the author of commit d3c6da6f87eedb20ea1591aaae1ea4e63d7bd777 ;-) > > Do you have any plan for dealing with the SS PHY and DP PHY conflicting > with each other? For example, PHY_MODE_CTRL needs to be "DP_MODE" for > 4-lane DP, "DP_MODE | USB3_MODE" for 2-lane DP + USB3, and (AFAIK) > "USB3_MODE" for superspeedplus usb (and it seems this gates some clocks, > so you can't read/write dp tx2 registers in 2-lane DP mode for example). Right. I've seen that behavior as well. > From your cover letter it sounds like this isn't relevant to your > hardware, but it looks like both PHYs are writing to the dp_com region > which is still problematic. (in the branch I linked, I disabled the SS > PHY to test the DP PHY) Right. I mentioned in the cover letter that this needs to hook into the type-c subsystem somehow. I haven't done any of that work because I don't have a configuration that is as dynamic. As long as the type-c stuff can express my static configuration it will be fine. If you have done any work there I'm happy to review the code and test it out on my configuration. The driver is setup for DP_MODE | USB3_MODE (i.e. concurrent mode) so it is already hardcoded for the 2-lane use case that I have. If I didn't connect two lanes from the phy to a USB hub I could support all the different combinations but that isn't the case. On phones it is basically the only case though because the pins from the usb3+dp phy go straight to the type-c connector. qcom_qmp_phy_com_init() is the only place I see the driver writing to it and it is refcounted so basically the first phy to get initialized will set things up in the common area. I suppose for supporting various use cases like 4 lanes DP or 2 lanes DP and USB then that refcounting logic will need to be changed. I'm not sure what is supposed to happen though. I guess the USB host controller, i.e. dwc3, will have to know to stop trying to use the phy and then power down and let the DP controller take over the phy? It's a dance of three or four drivers. > > Also some issues I noticed: > - used QSERDES_COM_RESETSM_CNTRL instead of > QSERDES_V3_COM_RESETSM_CNTRL2, which has different value > - in sc7180_dpphy_cfg, .regs is NULL, which results in NULL references Can you add these as inline review comments? Would help me understand what you're talking about. Thanks for the review!
