From: Peter Ujfalusi <peter.ujfal...@ti.com>

Add the intr, inta, ringacc and udmap nodes for main and mcu NAVSS.

Signed-off-by: Peter Ujfalusi <peter.ujfal...@ti.com>
Signed-off-by: Grygorii Strashko <grygorii.stras...@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 61 +++++++++++++++++++
 .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi      | 44 +++++++++++++
 2 files changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 70c8f7e941fb..cc4ff380a7bc 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -45,6 +45,31 @@
                #address-cells = <2>;
                #size-cells = <2>;
                ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+               ti,sci-dev-id = <199>;
+
+               main_navss_intr: interrupt-controller1 {
+                       compatible = "ti,sci-intr";
+                       ti,intr-trigger-type = <4>;
+                       interrupt-controller;
+                       interrupt-parent = <&gic500>;
+                       #interrupt-cells = <1>;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <213>;
+                       ti,interrupt-ranges = <0 64 64>,
+                                             <64 448 64>,
+                                             <128 672 64>;
+               };
+
+               main_udmass_inta: interrupt-controller@33d00000 {
+                       compatible = "ti,sci-inta";
+                       reg = <0x0 0x33d00000 0x0 0x100000>;
+                       interrupt-controller;
+                       interrupt-parent = <&main_navss_intr>;
+                       msi-controller;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <209>;
+                       ti,interrupt-ranges = <0 0 256>;
+               };
 
                secure_proxy_main: mailbox@32c00000 {
                        compatible = "ti,am654-secure-proxy";
@@ -56,6 +81,42 @@
                        interrupt-names = "rx_011";
                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                };
+
+               main_ringacc: ringacc@3c000000 {
+                       compatible = "ti,am654-navss-ringacc";
+                       reg =   <0x0 0x3c000000 0x0 0x400000>,
+                               <0x0 0x38000000 0x0 0x400000>,
+                               <0x0 0x31120000 0x0 0x100>,
+                               <0x0 0x33000000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       ti,num-rings = <1024>;
+                       ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <211>;
+                       msi-parent = <&main_udmass_inta>;
+               };
+
+               main_udmap: dma-controller@31150000 {
+                       compatible = "ti,j721e-navss-main-udmap";
+                       reg =   <0x0 0x31150000 0x0 0x100>,
+                               <0x0 0x34000000 0x0 0x100000>,
+                               <0x0 0x35000000 0x0 0x100000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt";
+                       msi-parent = <&main_udmass_inta>;
+                       #dma-cells = <1>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <212>;
+                       ti,ringacc = <&main_ringacc>;
+
+                       ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+                                               <0x0f>, /* TX_HCHAN */
+                                               <0x10>; /* TX_UHCHAN */
+                       ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+                                               <0x0b>, /* RX_HCHAN */
+                                               <0x0c>; /* RX_UHCHAN */
+                       ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+               };
        };
 
        main_pmx0: pinmux@11c000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi 
b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 670e4c7cd9fe..9ecb7e0c9cf7 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -81,4 +81,48 @@
                clocks = <&k3_clks 149 2>;
                clock-names = "fclk";
        };
+
+       cbass_mcu_navss: navss@28380000 {
+               compatible = "simple-mfd";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               dma-coherent;
+               dma-ranges;
+               ti,sci-dev-id = <232>;
+
+               mcu_ringacc: ringacc@2b800000 {
+                       compatible = "ti,am654-navss-ringacc";
+                       reg =   <0x0 0x2b800000 0x0 0x400000>,
+                               <0x0 0x2b000000 0x0 0x400000>,
+                               <0x0 0x28590000 0x0 0x100>,
+                               <0x0 0x2a500000 0x0 0x40000>;
+                       reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+                       ti,num-rings = <286>;
+                       ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <235>;
+                       msi-parent = <&main_udmass_inta>;
+               };
+
+               mcu_udmap: dma-controller@285c0000 {
+                       compatible = "ti,j721e-navss-mcu-udmap";
+                       reg =   <0x0 0x285c0000 0x0 0x100>,
+                               <0x0 0x2a800000 0x0 0x40000>,
+                               <0x0 0x2aa00000 0x0 0x40000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt";
+                       msi-parent = <&main_udmass_inta>;
+                       #dma-cells = <1>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <236>;
+                       ti,ringacc = <&mcu_ringacc>;
+
+                       ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
+                                               <0x0f>; /* TX_HCHAN */
+                       ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
+                                               <0x0b>; /* RX_HCHAN */
+                       ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
+               };
+       };
 };
-- 
2.17.1

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