Hi Alexandre, On 24/09/2020 15:08:21+0800, Alexandre Belloni wrote: > > Hi, > > On 24/09/2020 10:11:13+0800, Xiaoliang Yang wrote: > > INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3. > > You are changing GATE_STATE, not GATE_ENABLE Oh, sorry, it should be GATE_STATE field.
> > > This register is used by stream gate control of PSFP, and it has not > > been used before, because PSFP is not implemented in ocelot driver. > > > > Signed-off-by: Xiaoliang Yang <xiaoliang.yan...@nxp.com> > > --- > > include/soc/mscc/ocelot_ana.h | 8 ++++---- > > 1 file changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/include/soc/mscc/ocelot_ana.h > > b/include/soc/mscc/ocelot_ana.h index 841c6ec22b64..1669481d9779 > > 100644 > > --- a/include/soc/mscc/ocelot_ana.h > > +++ b/include/soc/mscc/ocelot_ana.h > > @@ -252,10 +252,10 @@ > > #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M > GENMASK(18, 16) > > #define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) > & GENMASK(18, 16)) >> 16) > > #define ANA_SG_CONFIG_REG_3_GATE_ENABLE > BIT(20) > > -#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << > 24) & GENMASK(27, 24)) > > -#define ANA_SG_CONFIG_REG_3_INIT_IPS_M > GENMASK(27, 24) > > -#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & > GENMASK(27, 24)) >> 24) > > -#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE > BIT(28) > > +#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << > 21) & GENMASK(24, 21)) > > +#define ANA_SG_CONFIG_REG_3_INIT_IPS_M > GENMASK(24, 21) > > +#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & > GENMASK(24, 21)) >> 21) > > +#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE > BIT(25) > > > > VSC7514 doesn't have the stream gate registers ans this was generated > automatically from the cml file for felix. Did that change? > > Seeing that bits in this register are not packed, I would believe your change > is > correct. Yes, this register is in VSC9959, we need it in PSFP gate control function for felix in future. I have tested on VSC9959, the bit offsets are not correct. Thanks, Xiaoliang Yang
