On Sun, Sep 27, 2020 at 4:30 PM Yingjoe Chen <yingjoe.c...@mediatek.com> wrote:
>
> On Fri, 2020-09-25 at 14:54 +0800, Ikjoon Jang wrote:
> > This patch enables 36bit dma address support to spi-mtk-nor.
> > Currently this is enabled only for mt8192-nor.
> >
> > Signed-off-by: Ikjoon Jang <i...@chromium.org>
> > ---
> >
> > (no changes since v1)
> >
> > drivers/spi/spi-mtk-nor.c | 18 +++++++++++++++++-
> > 1 file changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
> > index 8dbafee7f431..35205635ed42 100644
> > --- a/drivers/spi/spi-mtk-nor.c
> > +++ b/drivers/spi/spi-mtk-nor.c
> > @@ -78,6 +78,8 @@
> > #define MTK_NOR_REG_DMA_FADR 0x71c
> > #define MTK_NOR_REG_DMA_DADR 0x720
> > #define MTK_NOR_REG_DMA_END_DADR 0x724
> > +#define MTK_NOR_REG_DMA_DADR_HB 0x738
> > +#define MTK_NOR_REG_DMA_END_DADR_HB 0x73c
> >
> > /* maximum bytes of TX in PRG mode */
> > #define MTK_NOR_PRG_MAX_SIZE 6
> > @@ -106,6 +108,7 @@ struct mtk_nor {
> > unsigned int spi_freq;
> > bool wbuf_en;
> > bool has_irq;
> > + bool high_dma;
> > struct completion op_done;
> > };
> >
> > @@ -305,6 +308,11 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32
> > from, unsigned int length,
> > writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
> > writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
> >
> > + if (sp->high_dma) {
> > + writel(dma_addr >> 32, sp->base + MTK_NOR_REG_DMA_DADR_HB);
> > + writel((dma_addr + length) >> 32, sp->base +
> > MTK_NOR_REG_DMA_END_DADR_HB);
> > + }
> > +
>
> Maybe use upper_32_bits() ?
Thanks, good to know that!
>
>
> > if (sp->has_irq) {
> > reinit_completion(&sp->op_done);
> > mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
> > @@ -635,7 +643,8 @@ static const struct spi_controller_mem_ops
> > mtk_nor_mem_ops = {
> > };
> >
> > static const struct of_device_id mtk_nor_match[] = {
> > - { .compatible = "mediatek,mt8173-nor" },
> > + { .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
> > + { .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
> > { /* sentinel */ }
> > };
> > MODULE_DEVICE_TABLE(of, mtk_nor_match);
> > @@ -647,6 +656,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
> > void __iomem *base;
> > struct clk *spi_clk, *ctlr_clk;
> > int ret, irq;
> > + unsigned long dma_bits;
> >
> > base = devm_platform_ioremap_resource(pdev, 0);
> > if (IS_ERR(base))
> > @@ -660,6 +670,12 @@ static int mtk_nor_probe(struct platform_device *pdev)
> > if (IS_ERR(ctlr_clk))
> > return PTR_ERR(ctlr_clk);
> >
> > + dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
> > + if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
> > + dev_err(&pdev->dev, "failed to set dma mask(%lu)\n",
> > dma_bits);
> > + return -EINVAL;
> > + }
> > +
>
> As said in previous version. I don't see any place enable high_dma, so I
> think this patch won't set >32bits for anychip. We need something like:
>
> sp->hidh_dma = dma_bits > 32;
>
> Am I missing anything?
Yeah, you're right, that line disappeared between v2 ~ v3 (by mistake).
>
> Joe.C
>
