[PATCH v4 3/4] spi: spi-mtk-nor: support 36bit dma addressing

[Ikjoon Jang]

This patch enables 36bit dma address support to spi-mtk-nor.
Currently this is enabled only for mt8192-nor.

Signed-off-by: Ikjoon Jang <i...@chromium.org>
---

Changes in v4:
- Fix 0-day ci warning from shifting 32bit value
- Fix missing initialization of internal flags, 'high_dma'

 drivers/spi/spi-mtk-nor.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-mtk-nor.c b/drivers/spi/spi-mtk-nor.c
index cfb9a2450962..eac613b3930d 100644
--- a/drivers/spi/spi-mtk-nor.c
+++ b/drivers/spi/spi-mtk-nor.c
@@ -78,6 +78,8 @@
 #define MTK_NOR_REG_DMA_FADR           0x71c
 #define MTK_NOR_REG_DMA_DADR           0x720
 #define MTK_NOR_REG_DMA_END_DADR       0x724
+#define MTK_NOR_REG_DMA_DADR_HB                0x738
+#define MTK_NOR_REG_DMA_END_DADR_HB    0x73c
 
 #define MTK_NOR_PRG_MAX_SIZE           6
 // Reading DMA src/dst addresses have to be 16-byte aligned
@@ -102,6 +104,7 @@ struct mtk_nor {
        unsigned int spi_freq;
        bool wbuf_en;
        bool has_irq;
+       bool high_dma;
        struct completion op_done;
 };
 
@@ -278,6 +281,13 @@ static int mtk_nor_dma_exec(struct mtk_nor *sp, u32 from, 
unsigned int length,
        writel(dma_addr, sp->base + MTK_NOR_REG_DMA_DADR);
        writel(dma_addr + length, sp->base + MTK_NOR_REG_DMA_END_DADR);
 
+       if (sp->high_dma) {
+               writel(upper_32_bits(dma_addr),
+                      sp->base + MTK_NOR_REG_DMA_DADR_HB);
+               writel(upper_32_bits(dma_addr + length),
+                      sp->base + MTK_NOR_REG_DMA_END_DADR_HB);
+       }
+
        if (sp->has_irq) {
                reinit_completion(&sp->op_done);
                mtk_nor_rmw(sp, MTK_NOR_REG_IRQ_EN, MTK_NOR_IRQ_DMA, 0);
@@ -589,7 +599,8 @@ static const struct spi_controller_mem_ops mtk_nor_mem_ops 
= {
 };
 
 static const struct of_device_id mtk_nor_match[] = {
-       { .compatible = "mediatek,mt8173-nor" },
+       { .compatible = "mediatek,mt8192-nor", .data = (void *)36 },
+       { .compatible = "mediatek,mt8173-nor", .data = (void *)32 },
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_nor_match);
@@ -601,6 +612,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
        void __iomem *base;
        struct clk *spi_clk, *ctlr_clk;
        int ret, irq;
+       unsigned long dma_bits;
 
        base = devm_platform_ioremap_resource(pdev, 0);
        if (IS_ERR(base))
@@ -614,6 +626,12 @@ static int mtk_nor_probe(struct platform_device *pdev)
        if (IS_ERR(ctlr_clk))
                return PTR_ERR(ctlr_clk);
 
+       dma_bits = (unsigned long)of_device_get_match_data(&pdev->dev);
+       if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(dma_bits))) {
+               dev_err(&pdev->dev, "failed to set dma mask(%lu)\n", dma_bits);
+               return -EINVAL;
+       }
+
        ctlr = spi_alloc_master(&pdev->dev, sizeof(*sp));
        if (!ctlr) {
                dev_err(&pdev->dev, "failed to allocate spi controller\n");
@@ -639,6 +657,7 @@ static int mtk_nor_probe(struct platform_device *pdev)
        sp->dev = &pdev->dev;
        sp->spi_clk = spi_clk;
        sp->ctlr_clk = ctlr_clk;
+       sp->high_dma = (dma_bits > 32);
        sp->buffer = dmam_alloc_coherent(&pdev->dev,
                                MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
                                &sp->buffer_dma, GFP_KERNEL);
-- 
2.28.0.709.gb0816b6eb0-goog