[PATCH v2 01/10] ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml

[Zhen Lei]

1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same
   clock.

Signed-off-by: Zhen Lei <thunder.leiz...@huawei.com>
---
 arch/arm/boot/dts/hip01.dtsi    | 24 ++++++++++++------------
 arch/arm/boot/dts/hip04-d01.dts |  2 +-
 arch/arm/boot/dts/hip04.dtsi    |  6 +++---
 3 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi
index 975d39828405f0b..fd09e6d9309c755 100644
--- a/arch/arm/boot/dts/hip01.dtsi
+++ b/arch/arm/boot/dts/hip01.dtsi
@@ -41,41 +41,41 @@
                        compatible = "simple-bus";
                        ranges;
 
-                       uart0: uart@10001000 {
+                       uart0: serial@10001000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x10001000 0x1000>;
-                               clocks = <&hisi_refclk144mhz>;
-                               clock-names = "apb_pclk";
+                               clocks = <&hisi_refclk144mhz>, 
<&hisi_refclk144mhz>;
+                               clock-names = "baudclk", "apb_pclk";
                                reg-shift = <2>;
                                interrupts = <0 32 4>;
                                status = "disabled";
                        };
 
-                       uart1: uart@10002000 {
+                       uart1: serial@10002000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x10002000 0x1000>;
-                               clocks = <&hisi_refclk144mhz>;
-                               clock-names = "apb_pclk";
+                               clocks = <&hisi_refclk144mhz>, 
<&hisi_refclk144mhz>;
+                               clock-names = "baudclk", "apb_pclk";
                                reg-shift = <2>;
                                interrupts = <0 33 4>;
                                status = "disabled";
                        };
 
-                       uart2: uart@10003000 {
+                       uart2: serial@10003000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x10003000 0x1000>;
-                               clocks = <&hisi_refclk144mhz>;
-                               clock-names = "apb_pclk";
+                               clocks = <&hisi_refclk144mhz>, 
<&hisi_refclk144mhz>;
+                               clock-names = "baudclk", "apb_pclk";
                                reg-shift = <2>;
                                interrupts = <0 34 4>;
                                status = "disabled";
                        };
 
-                       uart3: uart@10006000 {
+                       uart3: serial@10006000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x10006000 0x1000>;
-                               clocks = <&hisi_refclk144mhz>;
-                               clock-names = "apb_pclk";
+                               clocks = <&hisi_refclk144mhz>, 
<&hisi_refclk144mhz>;
+                               clock-names = "baudclk", "apb_pclk";
                                reg-shift = <2>;
                                interrupts = <0 4 4>;
                                status = "disabled";
diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts
index 9019e0d2ef60b67..f5691dbc26d2419 100644
--- a/arch/arm/boot/dts/hip04-d01.dts
+++ b/arch/arm/boot/dts/hip04-d01.dts
@@ -22,7 +22,7 @@
        };
 
        soc {
-               uart0: uart@4007000 {
+               uart0: serial@4007000 {
                        status = "ok";
                };
        };
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 555bc6b6720fc94..bccf5ba3d8553c2 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -250,12 +250,12 @@
                                     <0 79 4>;
                };
 
-               uart0: uart@4007000 {
+               uart0: serial@4007000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x4007000 0x1000>;
                        interrupts = <0 381 4>;
-                       clocks = <&clk_168m>;
-                       clock-names = "uartclk";
+                       clocks = <&clk_168m>, <&clk_168m>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        status = "disabled";
                };
-- 
1.8.3