Hi Andrew: On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote: > > > > > Do you really mean PHY? I actually expect it is PCS? > > > > > > > > For this implementation, yes. > > > > > > Yes, you have a PHY? Or Yes, it is PCS? > > > > Sorry, I mean I have a PHY. > > > > > > > > To me, the phylib maintainer, having a PHY means you have a base-T > > > interface, 25Gbase-T, 40Gbase-T? That would be an odd and expensive > > > architecture when you should be able to just connect SERDES interfaces > > > together. > > You really have 25Gbase-T, 40Gbase-T? Between the FPGA & XL710? > What copper PHYs are using? > > > I see your concerns about the SERDES interface between FPGA & XL710. > > I have no concerns about direct SERDES connections. That is the normal > way of doing this. It keeps it a lot simpler, since you don't have to > worry about driving the PHYs. >
I did some investigation and now I have some details. The term 'PHY' described in Ether Group Spec should be the PCS + PMA, a figure below for one configuration: +------------------------+ +-----------------+ | Host Side Ether Group | | XL710 | | | | | | +--------------------+ | | | | | 40G Ether IP | | | | | | | | | | | | +---------+ | | XLAUI | | | | MAC - |PCS - PMA| | |----------| PMA - PCS - MAC | | | +---------+ | | | | +-+--------------------+-+ +-----------------+ Thanks, Yilun
