On 30/10/20 01:31PM, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthe...@linux.intel.com>
>
> On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
> Direct Access Controller(DAC).
>
> This patch adds a quirk to disable the Direct Access Controller
> for data transfer instead it uses indirect data transfer.
>
> Signed-off-by: Ramuthevar Vadivel Murugan
> <vadivel.muruganx.ramuthe...@linux.intel.com>
> ---
> drivers/spi/spi-cadence-quadspi.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/spi/spi-cadence-quadspi.c
> b/drivers/spi/spi-cadence-quadspi.c
> index d7b10c46fa70..6d6f7c440ece 100644
> --- a/drivers/spi/spi-cadence-quadspi.c
> +++ b/drivers/spi/spi-cadence-quadspi.c
> @@ -1107,6 +1107,13 @@ static void cqspi_controller_init(struct cqspi_st
> *cqspi)
> writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
>
> cqspi_controller_enable(cqspi, 1);
> +
> + /* Disable direct access controller */
> + if (!cqspi->use_direct_mode) {
> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> + reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> + }
You did not address my comment here from last time around [0]. Please
replace this hunk with the one below and test it. Also mention in the
commit message that the DAC bit resets to 1 so there is no need to
explicitly set it.
--- 8< ---
diff --git a/drivers/spi/spi-cadence-quadspi.c
b/drivers/spi/spi-cadence-quadspi.c
index d7ad8b198a11..d2c5d448a944 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -2156,10 +2156,12 @@ static void cqspi_controller_init(struct cqspi_st
*cqspi)
writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
- /* Enable Direct Access Controller */
- reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
- reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
- writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ /* Disable Direct Access Controller */
+ if (!cqspi->use_dac_mode) {
+ reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
+ reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+ writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
+ }
cqspi_controller_enable(cqspi, 1);
}
--- >8 ---
Same disclaimer as last time: not tested at all.
[0] https://lore.kernel.org/linux-spi/20201022090146.2uj5gfx73dsfu...@ti.com/
PS: Please Cc me in the next revision. I missed 3 revisions in between
because I'm not subscribed to this list. Otherwise I would have sent
this much sooner :-)
> }
>
> static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
> @@ -1388,6 +1395,10 @@ static const struct cqspi_driver_platdata am654_ospi =
> {
> .quirks = CQSPI_NEEDS_WR_DELAY,
> };
>
> +static const struct cqspi_driver_platdata intel_lgm_qspi = {
> + .quirks = CQSPI_DISABLE_DAC_MODE,
> +};
> +
> static const struct of_device_id cqspi_dt_ids[] = {
> {
> .compatible = "cdns,qspi-nor",
> @@ -1403,6 +1414,7 @@ static const struct of_device_id cqspi_dt_ids[] = {
> },
> {
> .compatible = "intel,lgm-qspi",
> + .data = &intel_lgm_qspi,
> },
> { /* end of table */ }
> };
> --
> 2.11.0
>
--
Regards,
Pratyush Yadav
Texas Instruments India
