On Fri, Nov 6, 2020 at 12:08 PM Srinivas Kandagatla <[email protected]> wrote:
> Some more detail of wiring of this additional pin-controller IP: > > This IP is an additional pinctrl block on top the existing SoC TLMM > pin-controller (Audio) pins. > > The hw setup looks like: > > TLMM GPIO[146 - 159] --> LPASS LPI GPIO [0 - 13] > > However SoC TLMM pin-controller can only be touched for use of those > pins in GPIO mode and non gpio mode is completely handled by the LPASS > LPI pinctrl block. Apart from this slew rate is also available in this > block for certain pins which are connected to SLIMbus or SoundWire Bus. OK put this in the commit message, good to know! I gues the pins are not quite "GPIO" at this point, instead they are turned into LPASS pins? > Normally we would not expect these pins to be touched by SoC TLMM > pin-controller as these pins are used for audio usecase and the control > is always with LPASS LPI controller. There are additional bits to > configure/enforce this in SoC TLMM block! If you start to use IRQs they might become hierarchical WRT the TLMM. But no IRQ support yet, so... Yours, Linus Walleij
