On Mon, Nov 30, 2020 at 05:07:09PM +0000, Vincenzo Frascino wrote: > UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing > compilation issues when trying to implement in kernel MTE async > mode. > > Fix the macro correcting the typo. > > Note: MTE async mode will be introduced with a future series. > > Fixes: c058b1c4a5ea ("arm64: mte: system register definitions") > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Will Deacon <w...@kernel.org> > Signed-off-by: Vincenzo Frascino <vincenzo.frasc...@arm.com> > --- > arch/arm64/include/asm/sysreg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e2ef4c2edf06..801861d05426 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -987,7 +987,7 @@ > #define SYS_TFSR_EL1_TF0_SHIFT 0 > #define SYS_TFSR_EL1_TF1_SHIFT 1 > #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) > -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT) > +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT)
I think we should first rename it to EU and then fix it properly ;). While nothing breaks without this patch currently, we should merge it as a fix. Acked-by: Catalin Marinas <catalin.mari...@arm.com> Thanks.