Sorry for top posting but I need the help of the irqchip maintainer Marc Z to hash this out.
The mask/unmask/disable/enable semantics is something that you need to work with every day to understand right. Yours, Linus Walleij On Mon, Nov 30, 2020 at 10:36 AM Luo Jiaxing <luojiax...@huawei.com> wrote: > > The mask and unmask registers are not configured in dwapb_irq_enable() and > dwapb_irq_disable(). In the following situations, the IRQ will be masked by > default after the IRQ is enabled: > > mask IRQ -> disable IRQ -> enable IRQ > > In this case, the IRQ status of GPIO controller is inconsistent with it's > irq_data too. For example, in __irq_enable(), IRQD_IRQ_DISABLED and > IRQD_IRQ_MASKED are both clear, but GPIO controller do not perform unmask. > > Signed-off-by: Luo Jiaxing <luojiax...@huawei.com> > --- > drivers/gpio/gpio-dwapb.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c > index 2a9046c..ca654eb 100644 > --- a/drivers/gpio/gpio-dwapb.c > +++ b/drivers/gpio/gpio-dwapb.c > @@ -270,6 +270,8 @@ static void dwapb_irq_enable(struct irq_data *d) > u32 val; > > spin_lock_irqsave(&gc->bgpio_lock, flags); > + val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d)); > + dwapb_write(gpio, GPIO_INTMASK, val); > val = dwapb_read(gpio, GPIO_INTEN); > val |= BIT(irqd_to_hwirq(d)); > dwapb_write(gpio, GPIO_INTEN, val); > @@ -284,6 +286,8 @@ static void dwapb_irq_disable(struct irq_data *d) > u32 val; > > spin_lock_irqsave(&gc->bgpio_lock, flags); > + val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d)); > + dwapb_write(gpio, GPIO_INTMASK, val); > val = dwapb_read(gpio, GPIO_INTEN); > val &= ~BIT(irqd_to_hwirq(d)); > dwapb_write(gpio, GPIO_INTEN, val); > -- > 2.7.4 >
