On Mon, 07 Dec 2020 10:31:46 +0100 Jerome Brunet wrote: > > The m250_sel mux clock uses bit 4 in the PRG_ETH0 register. Fix this by > > shifting the PRG_ETH0_CLK_M250_SEL_MASK accordingly as the "mask" in > > struct clk_mux expects the mask relative to the "shift" field in the > > same struct. > > > > While here, get rid of the PRG_ETH0_CLK_M250_SEL_SHIFT macro and use > > __ffs() to determine it from the existing PRG_ETH0_CLK_M250_SEL_MASK > > macro. > > > > Fixes: 566e8251625304 ("net: stmmac: add a glue driver for the Amlogic > > Meson 8b / GXBB DWMAC") > > Signed-off-by: Martin Blumenstingl <martin.blumensti...@googlemail.com> > > Reviewed-by: Jerome Brunet <jbru...@baylibre.com>
Applied, thanks!