* H. Peter Anvin <[EMAIL PROTECTED]> wrote:
> I believe this will suffer from the issue that was raised: this will
> use udelay() long before loop calibration (and no, we can't just "be
> conservative" since there is no "conservative" value we can use.)
>
> Worse, I suspect that at least the PIT, which may need to be used for
> udelay calibration, is one of the devices that may be affected. I
> have seen the Verilog for a contemporary chipset, and it can only
> access the PIT once per microsecond -- this actually has to do with
> the definition of the PIT; some of the PIT operations are ill-defined
> if allowed at a higher frequency than the PIT clock.
i think the native_io_delay() in quirks.c signals the obvious solution:
a DMI (or otherwise) driven quirk that activates a port 0x80 based delay
on such boards. Combined with an iodelay=port80 boot option as well
perhaps, just in case someone hits a system that is not blacklisted yet.
This way such crazy broken hardware can be mapped correctly - like we
map such quirks in every other case. Perhaps even do this workaround on
the PIT driver level. Instead of perpetuating the superstition of port
80 forever.
Ingo
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